A Low-Power Sense Amplifier-Based Flip-Flop Using a Conditional Capture Method

A novel sense amplifier-based flip-flop (SAFF) is proposed for low-power operation. Since setup time is a key timing metric of a flip-flop, SAFF structures with near-zero setup time are advantageous for high-speed applications. However, reducing D-Q delay by increasing transistor size generally increases internal-node switching and power consumption. To address this trade-off, a conditional capture method using a modified NOR gate is proposed. The modified NOR gate compares D and Q and activates