Semiconductor Engineering

Researchers from Politecnico di Milano and STMicroelectronics published a technical paper titled “Event-Driven Reinforcement Learning Enables Long-Horizon Control in Semiconductor Fabrication.” The paper proposes a deep reinforcement learning framework for multi-objective policy optimization in semiconductor manufacturing, where heterogeneous wafers move through hundreds of process steps across c…

Researchers from Rochester Institute of Technology published a technical paper titled “MIPSBLEED: Uncovering Microarchitectural Timing Leaks in Pervasive Embedded Processors.” Excerpt from abstract “This paper exposes how Simultaneous Multithreading (SMT), a feature increasingly used to boost performance in these environments, creates powerful cross-core timing channels on MIPS-based platforms. W…

Researchers from University of California, Riverside and Futurewei published a technical paper titled “LLM4RTL: Tool-Assisted LLM for RTL Generation.” Abstract: “Large language models (LLMs) have facilitated impressive progress in software engineering, code generation, tooling, and systems. Concurrently, a significant body of research has developed which explores a growing variety of methods and …

Apple-Intel is on, says Trump; Amkor's big win; Intel 18A-P; Amazon to sell its AI chips; Rambus' automotive RoT; Brewer's buy; VLSI Symposium tech; CHIPS Act funding; MIT sensor; RISC-V CPU fuzzing. The post Chip Industry Week In Review appeared first on Semiconductor Engineering .

A robust OBGA packaging solution for automotive-grade reliability. The post Scaling ADAS To 10+ Cameras appeared first on Semiconductor Engineering .

Overcoming manufacturing variation at advanced nodes. The post Accelerating GAA Logic Yield Optimization With Digital Twins appeared first on Semiconductor Engineering .

Hybrid bonding permits unprecedented connection density. The post How To Build Billions of Bumps appeared first on Semiconductor Engineering .

Higher performance, backside power, and new materials. The post VLSI 2026: Intel 18A Platform Momentum From Devices To Routed Designs appeared first on Semiconductor Engineering .

Demand for better pattern fidelity and the adoption of ILT are increasing pressure to shift to curvilinear mask technology. The post A New Fracture Engine For Curvilinear Masks And MULTIGON Mask Data appeared first on Semiconductor Engineering .

Get the advantages of wafer randomization without extra equipment, cost or slowdown The post Randomizing Wafers To Zero In On Process Problems Much Faster appeared first on Semiconductor Engineering .

How to automate bump and TSV planning, visualization, and analysis, and also manage millions of interconnects while improving productivity. The post How to Create Efficient Bump and TSV Plans for Multi-Die Designs appeared first on Semiconductor Engineering .

Supports higher throughput, reduced cycle time, and lower cost per package, while enabling integration of increasingly complex multi-die architectures. The post Automated 310mm Panel-Level Packaging to Accelerate AI Innovation: Tech Brief appeared first on Semiconductor Engineering .

Why new designs and process flows could help overcome manufacturing challenges. The post GaN Power Devices Go Vertical appeared first on Semiconductor Engineering .

Key Takeaways: System-level energy and bandwidth pressures are pulling optics into the package faster than the manufacturing flow can mature. Photonics combines front-end fabrication, materials, thermal, cleanliness, and test into one problem that can’t be solved domain by domain. Test is moving upstream because discovering an optical failure after final assembly forfeits every good component... …

When is a complex chip design ready to be shipped to manufacturing? The post Signoff Of Synthesis-Optimized Registers appeared first on Semiconductor Engineering .

On-die monitors, localized analytics, and lifecycle data are giving architects new ways to close the gap between design intent and silicon behavior. The post Designing Chips That Can Explain Themselves appeared first on Semiconductor Engineering .

NVMe on-controller memory; SSN datapaths; Git-based chip workflows; low-light image enhancement; testing AI networks. The post Blog Review: June 17 appeared first on Semiconductor Engineering .

Researchers from Google and University of California, Berkeley published a technical paper titled “Google’s Training Supercomputers from TPU v2 to Ironwood: Architectural Stability, Scale, Resilience, Power Efficiency, and Sustainability Across Five Generations.” The paper summarizes five generations of Google TPUs, from TPU v2 through Ironwood, and examines how the systems evolved into scalable,…

Multi-GPU traffic modeling; physical neural computing; RISC-V fault injection; automotive CAN timing analysis; EUV source optimization; lithography defect detection; dual-beam EUV efficiency. The post Chip Industry Technical Paper Roundup: June 16 appeared first on Semiconductor Engineering .

Researchers from University of Wisconsin-Madison and AMD Research and Advanced Development published a technical paper titled “Eidola: Modeling Multi-GPU Network Communication Traffic in Distributed AI Workloads.” Abstract: “As distributed AI workloads grow in scale, multi-GPU systems have become essential for training large models. Although techniques like kernel fusion and overlapping communica…