Wafer-edge uniformity in semiconductor etching is a key quality metric directly linked to device yield and is strongly governed by the local sheath structure near the wafer edge-focus ring boundary. However, the relative effects of focus ring geometry, dielectric material, and applied voltage waveform on edge ion transport have not been systematically compared. In this study, a two-dimensional particle-in-cell/Monte Carlo collision (PIC/MCC) simulation was performed for an argon capacitively coupled plasma to examine how focus ring height (15-26 mm), electrode-to-focus ring gap width (4-10 mm), dielectric permittivity (4.0 for quartz and 10.3 for Al2O3), and low frequency (LF) voltage affect plasma behavior and ion transport near the wafer edge. The voltage waveform effect was evaluated by comparing an HF-only single frequency (SF) condition, a baseline pulsed dual-frequency (Pulsed DF) condition with VLF=-1000 V and VHF=300 V, and an enhanced pulsed DF condition with VLF=-2000 V. Focus ring height and gap width were found to control edge ion incidence more directly than dielectric permittivity. A focus ring height matched to the powered electrode minimized sheath distortion and produced near-normal ion incidence, whereas a larger electrode-to-focus ring gap broadened the ion angular distribution. Increasing the relative permittivity from 4.0 to 10.3 modified the local electric field structure and reduced the outward ion flux near the focus ring but had only a modest effect on the overall plasma density. Under fixed focus ring geometry, increasing the LF voltage level strongly modified the wafer edge ion energy-angle distribution: the SF condition confined ions to a relatively narrow low-energy range near 200 eV, whereas the enhanced pulsed DF condition extended the ion energy to approximately 1400 eV. These results indicate that focus ring height and gap width are the primary design variables for controlling wafer edge ion incidence, while voltage waveform optimization is also required to control ion energy and improve wafer edge process uniformity.