To address inherent frequency drift, nonlinear bias and time-varying errors of satellite-borne hardware clock circuits, this study develops an intelligent clock bias correction approach built on the CI-PatchTST-TCN-Attention-GRU hybrid network. First, a time-decay weighted least squares polynomial fitting method is used to decompose the slow hardware aging drift from raw clock measurements. For high-frequency stochastic residual modeling, Reversible Instance Normalization (ReVIN) and patch segmentation are applied to extract channel-independent features while retaining local temporal characteristics. The TCN-Attention-GRU submodule further captures long-range temporal correlations and dynamic fluctuation patterns of residual sequences via dilated convolution, multi-head self-attention and gated recurrent units. Validated with real BDS-3 precise clock offset data, the proposed method mitigates on-board timing drift and improves the long-term stability of timing modules. It achieves higher prediction accuracy than conventional benchmark models and maintains stable performance under limited training data.