SIGARCH

This is the second (and final) post in the series covering the Next Generation Branch Prediction Champtionship (CBP-NG). Part-I details the provided infrastructure and the winning submissions. Distilled Branch Predictors (Simha Sethumadhavan – Columbia University) The author proposes an ‘Ensemble Predictor’ composed of a fast, one-cycle predictor P1 and a slower (but more accurate) two-cycle […]

Background The Next Generation Branch Prediction Championship (CBP-NG) aimed to address practical implementation challenges in branch prediction, moving beyond metrics used in earlier iterations. By emphasizing energy-adjusted performance—incorporating throughput, timing, and dynamic energy alongside traditional Misprediction Per Kilo-Instruction (MPKI) metrics—the championship sought to align re…

Zero-Knowledge Proofs As conversations about LLMs continue to dominate computer science, the cryptographic community has been abuzz around a different three letter acronym: ZKP. Zero-Knowledge Proofs (ZKPs) allow a prover to convince a verifier that a statement is true without revealing the secret information that makes it true. In other words, ZKPs make it possible […]

LLM execution requires moving gigabytes of data, which includes static model weights, the generated KV cache, and other intermediate representations. Depending on the deployment, this may involve communication across the network, PCIe links, accelerator links (e.g., NVLink), and memory interconnects, often leaving LLM execution bottlenecked by the data movement feeding it. An obvious mitigation f…

AI is starting to shape architectural mechanisms, workloads, and evaluation. To make sense of it, we need a compact, shared way to preserve enough of that process for other groups to evaluate and build on AI-assisted claims. At the 53rd ISCA in Raleigh, AI for architecture stopped feeling like a side conversation. In the hallways, […]

The conference The 53rd International Symposium on Computer Architecture (ISCA) was held at the Raleigh Convention Center in Raleigh, North Carolina, from June 27 to July 1, 2026. Raleigh sits at one corner of the Research Triangle, anchored by North Carolina State University, the University of North Carolina at Chapel Hill, and Duke University. General […]

The Return of Rigorous Full-System Timing Simulation Accurate timing simulation remains one of the most important tools in computer architecture, but modern systems have made cycle-level simulation increasingly impractical. Today’s platforms combine many-core CPUs, deep memory hierarchies, accelerators, complex I/O, and large software stacks, making detailed simulation extremely slow—often requir…

When an agent makes an incorrect guess, the obvious mistakes like bad files or stale outputs are straightforward to see. However, there are less visible leaks that pose significant risks, such as timing patterns or cached context. The context and data exchanged between tools, services, and third-party systems can also be problematic. This situation becomes particularly concerning when AI agents t…

Architecture & Systems are Changing: The Architect’s Role in the Era of Agentic Co-Design The AI datacenter stack is built on hardware-software contracts and abstractions that were never designed for the workloads datacenters now serve. Memory systems strain under terabyte-scale capacity. Heterogeneous accelerators have been pressed into deployment. With datacenters projected to consume over 1,00…

TL;DR: The history of parallel computing is a history of shifting what we put at the center of the computer. The first axis, control-level parallelism (CLP), is control-centric and schedules around the program counter: it gave us the high-performance computing (HPC) era. The second axis, data-level parallelism (DLP), is data-centric and schedules around tensors: it […]

Editor’s Note: this post is a republication of CRA-I post available at: https://cra.org/industry/2026/04/27/how-ai-will-reshape-computer-systems-by-2035-a-jeffersonian-dinner-in-san-francisco-about-our-10000x-future/ CRA-Industry (CRA-I) recently continued its series of intimate Industry Salon Gatherings, bringing together leaders to discuss the long-term trajectory of our field. Our latest sessi…

This article continues (and concludes) the discussion on the proceedings of DPC-4, covering the remaining four contestants and a summary of the trends observed in all eight prefetchers presented in the championship. Similar to Part I, we focus on how each prefetch algorithm functions, and why it is effective. Finer implementation details can be obtained […]

This article is the first in a two-part series that summarizes the key contributions of 4th Data Prefetching Championship (DPC-4), held in conjunction with the 32nd iteration of HPCA in 2026. While discussing innovative data prefetching techniques presented in this contest, we focus on the functionality of proposed algorithms and also explain why they are […]

Hybrid continuous-discrete-variable (CV-DV) quantum computing combines oscillators and qubits to tackle problems that are difficult for either model alone, from bosonic simulation to quantum error correction. At ASPLOS 2026, our tutorial introduced the foundations, compilation stack, benchmarking methods, and programming tools behind this emerging architecture model. In this blog post, we overvie…

For decades, we have designed chips in fundamentally the same way: human intuition applied to a vanishingly small slice of an impossibly large design space. That paradigm worked when Moore’s Law was lifting everything. We could afford to be wrong. We could afford to miss the best design. Process scaling would close the gap. That […]

Years ago, I came across three pioneering works (CSI-NN, Cache Telepathy, and DeepSniffer) in the field of reverse engineering neural networks that inspired my journey into side-channel attacks to uncover the secrets of modern Deep Neural Networks (DNNs). Fast forward to today, and there has been significant exploitation of side-channel attacks to discover the secrets of neural networks. It’s a g…

The debate of sparsity versus quantization has made its rounds in the ML optimization community for many years. Now, with the Generative AI revolution, the debate is intensifying. While these might both seem like simple mathematical approximations to an AI researcher, for a hardware architect, they present fundamentally different sets of challenges. Many architects in the AI hardware space are de…

As we close the book on 2025, Computer Architecture Today has seen another successful year of community engagement. We published 29 posts covering a wide spectrum of topics—from datacenter energy-efficiency to the evolving debate on LLMs in peer review, alongside trip reports from our major conferences. I want to thank all our authors for their insights, with special appreciation for those who co…

Large language model (LLM) agents are quickly moving from “single agent” to *multi-agent systems*: tool-using agents, planner-orchestrator, debate teams, specialized sub-agents that collaborate to solve tasks. At the same time, the *context* these agents must operate within is becoming more complex: longer histories, multiple modalities, structured traces, and customized environments. This combin…

TL;DR: Latency-tolerant architectures, e.g., GPUs, increasingly use memory/storage hierarchies, e.g., for KV Caches to speed Large-Language Model AI inference. To aid codesign of such workloads and architectures, we develop the simple PipeOrgan analytic model for bandwidth-bound workloads running on memory/storage hierarchies. Background For three reasons, memory bandwidth, more than latency, lim…